Phase-locked loops (PLLs) perform functions that are critical to many of today's electronic circuits. For example, a PLL can generate one or more output signals, hereinafter oscillator signals, that are phase locked to a reference signal, and thus have frequencies that are precise multiples of the reference signal's frequency. One can use such a PLL oscillator signal to clock digital circuits or to modulate/demodulate data signals in an electronic system.
Unfortunately, the higher the data rate of a signal that modulates a PLL oscillator signal, the more sensitive the modulated signal is to noise. That is, for a given level of noise, the Signal-to-Noise Ratio (SNR) of the modulated signal decreases as the data rate of the modulating signal increases.
FIG. 1 is a block diagram of conventional PLL 10 that, when operating in a locked mode, generates two oscillator signals OSC1 and OSC2 that are phase locked to a reference signal REF. The PLL 10 includes a phase detector 12 for detecting a difference Δφ between the phases of REF and a feedback oscillator signal and for generating a phase-correction pulse having a duration that is related to the phase difference Δφ. A control circuit 14 filters the phase-correction pulse and generates a control signal from the filtered phase-correction pulse, and a signal-controlled oscillator, here a voltage-controlled oscillator (VCO) 16, generates OSC1 having a frequency that is steered by the control signal. When the feedback signal is locked to REF—that is, the feedback signal is in phase with REF such that Δφ=0—the VCO 16 generates OSC1 having a frequency of F×T, where F is the frequency of REF. A forward frequency divider 18 generates OSC2 by frequency dividing OSC1 by M, and a feedback frequency divider 20 generates the feedback signal by frequency dividing OSC2 by N=T/M. Consequently, when the feedback signal is phase locked to REF, OSC2 has a frequency of F×T/M, and the feedback signal has the same frequency, F, as REF.
During a locked mode of operation, the PLL 10 phase locks OSC1 and OSC2 to REF by using negative feedback to maintain the phase difference Δφ between REF and the feedback oscillator signal at or near zero. For example, assume that during one cycle the feedback signal lags REF such that Δφ is negative. Therefore, to close the phase gap, the PLL 10 increases the frequency of the feedback signal by increasing the frequency of OSC1. Specifically, the phase detector 12 generates a phase-correction pulse that indicates that the feedback signal lags REF. In response to the phase-correction pulse, the control circuit 14 speeds up the VCO 16 to increase the frequencies of OSC1 and OSC2, and to thus increases the frequency of the feedback signal. When the frequency of the feedback signal increases to the point where the feedback signal is in phase with REF, the phase-correction pulse indicates that Δφ=0 (no correction is necessary) such that the control circuit 14 maintains the feedback signal at the in-phase frequency. If the feedback signal leads REF such that Δφ is positive, the PLL 10 decreases the frequency of the feedback signal. Specifically, the phase detector 12 generates the phase-correction pulse to indicate that the feedback signal leads REF. In response to the phase-correction pulse, the control circuit 14 slows down the VCO 16 to decrease the frequencies of OSC1 and OSC2, and to thus decrease the frequency of the feedback signal. When the frequency of the feedback signal decreases to the point where the feedback signal is in phase with REF, the phase-correction pulse indicates that Δφ=0 (no correction is necessary) such that the control circuit 14 maintains the feedback signal at the in-phase frequency.
Unfortunately, as discussed above and as discussed below in conjunction with FIGS. 2-4, the inventor has discovered that noise generated by the control circuit 14, an imbalance in the control circuit, or both control-circuit noise and imbalance, may introduce a phase error into OSC1 and OSC2, and this phase error may reduce the SNR of a modulated data signal that includes OSC1 or OSC2 as a carrier component or of a data signal that is demodulated by OSC1 or OSC2.
FIG. 2 is a schematic diagram of the phase detector 12 and the control circuit 14 of FIG. 1.
The phase detector 12 includes a phase-detect circuit 30 and a reset circuit 32. The phase-detect circuit 30 includes a pair of D flip-flops 34 and 36 for detecting the phase difference Δφ between the feedback signal and REF, for generating oscillator-frequency-UP and oscillator-frequency-DOWN phase-detect pulses in response to the detected Δφ, and for providing these phase—detect pulses to the control circuit 14 as the phase—correction pulses. Specifically, in response to REF transitioning from a logic 0 to a logic 1, the flip-flop 34 generates a logic 1 for UP. Likewise, in response to the feedback signal transitioning from a logic 0 to a logic 1, the flip-flop 36 generates a logic 1 for DOWN. Consequently, if UP transitions to logic 1 before DOWN transitions to logic 1, the feedback signal lags REF by a phase difference Δφlag that is proportional to the time difference between the logic-1 transitions of UP and DOWN. Conversely, if UP transitions to logic 1 after DOWN, the feedback signal leads REF by a phase difference Δφlead that is proportional to the time difference between the logic-1 transitions of UP and DOWN. Moreover, if UP and DOWN transition to logic 1 at the same time, the feedback signal is in phase with REF, i.e., Δφ=0, for that cycle. The reset circuit 32 includes an AND gate 38 that generates a RESET signal for resetting the flip-flops 34 and 36 after the lagging one of the pulses UP and DOWN transitions to a logic 1. The reset flip-flops 34 and 36 are then ready for the next logic-1-to-logic-0 transitions of REF and the feedback signal.
The control circuit 14 includes a charge pump 40 that generates a control voltage CV across a capacitor 42 in response to the UP and DOWN phase-detect pulses from the phase detector 12. The VCO 16 (FIG. 1) is designed such that the frequency of OSC1 is proportional to CV. Therefore, as CV increases, the frequency of OSC1 increases, and as CV decreases, the frequency of OSC1 decreases. Consequently, in response to the UP pulse (the feedback signal lags REF), the charge pump 40 generates a charge current Iup to increase CV, and in response to the DOWN pulse (the feedback signal leads REF), the pump generates a discharge current Idown to reduce CV.
FIGS. 3 and 4 are timing diagrams of the following signals in FIGS. 1 and 2 when the PLL 10 is operating in a locked mode: RESET, REF, the feedback signal, DOWN, and UP. Specifically, FIG. 3 is a timing diagram of these signals when the feedback signal is in phase with REF (Δφ=0), and FIG. 4 is a timing diagram of these signals when the feedback signal leads REF by Δφlead≈1 nanosecond (ns).
Referring to FIGS. 2 and 3, even when the feedback signal is in phase with REF, the phase-detect circuit 30 generates both UP and DOWN having active logic-1 levels during an “overcorrection” period. At time t0, both REF and the feedback signal transition to a logic 1, and thus are in phase with one another. Therefore, one might expect that the phase-detect circuit 30 would not transition UP or DOWN to an active logic 1 because no phase correction is needed. But because of delays inherent in the phase-detect and reset circuits 30 and 32, this is not the case. At time t1, both UP and DOWN transition to logic 1, where the delay—here approximately 1 ns—between t0 and t1 is due to the respective clocking-propagation delays through the flip-flops 34 and 36. Because the flip-flops 34 and 36 are typically on the same area of the chip (not shown) that incorporates them, it is accurate to assume that their delays are equal or approximately equal. At time t2, RESET transitions to an active logic 1, where the delay—here approximately 0.1 ns—between t1 and t2 is the output-logic-0-to-logic-1 propagation delay through the AND gate 38. At time t3, UP and DOWN transition back to an inactive logic 0, where the delay—here approximately 0.7 ns—between t2 and t3 is the clearing-propagation delay through the flip-flops 34 and 36. The period between t1 and t3—here approximately 0.8 ns—is the overcorrection period, which is the nonzero, and ideally unnecessary, period that UP and DOWN are active after no further phase correction of the feedback signal is necessary. Although the flip-flops 34 may have different clearing-propagation delays that may cause mismatched overcorrection periods by causing UP and DOWN to transition to logic 0 at different times, such a mismatch is typically so small that it can be ignored. At time t4, RESET transitions back to an inactive logic 0, where the delay—here approximately 0.3 ns—between t3 and t4 is the output-logic-1-to-logic-0 propagation delay through the AND gate 38.
Still referring to FIGS. 2 and 3, the inventor has discovered that the overcorrection period may cause the charge pump 40 to introduce a phase error into OSC1 and OSC2. When both UP and DOWN are active the charge pump 40 simultaneously generates both Iup and Idown. Ideally, the charge pump 40 is balanced (Iup=Idown) such that when both UP and DOWN are active, the net current to the capacitor 42 is zero, CV remains unchanged, and thus the phases of OSC1 and OSC2 remain unchanged. But manufacturing variations in the circuitry of the control circuit 14 may cause the pump 40to be unbalanced (Iup=Idown). Consequently, the unbalanced pump 40 may erroneously change CV, and thus the phases of OSC1 and OSC2, during the overcorrection period. Furthermore, the charge pump 40 typically generates noise when it is active, and this noise may cause an erroneous shift in the phases of OSC1 and OSC2 independently of any shift that a pump imbalance may cause. In both the imbalance and noise cases, however, the phase error that the pump 40 introduces to OSC1 and OSC2 is proportional to the length of the overcorrection period. That is, the longer the overcorrection period, the greater the phase error that the charge pump 40 typically introduces to OSC1 and OSC2.
Referring to FIGS. 2 and 4, the overcorrection period, and the corresponding phase error that the charge pump 40 may introduce, are also present when REF and the feedback signal are out of phase. At time t0 the leading feedback signal transitions to a logic 1, and thus triggers a true phase-correction cycle. At time t1 the flip-flop 36 transitions DOWN to logic 1 in response to the feedback signal's transition, and REF transitions to logic 1. One might expect that the phase-detect circuit 30 would transition DOWN back to logic 0 and not transition UP to an active logic 1 because no further phase correction is needed. But because of the above-described delays inherent in the phase-detect and reset circuits 30 and 32, this is not the case. At time t2, the flip-flop 34 transitions UP to logic 1 in response to REF's transition, and, at time t3, the AND gate 38 transitions RESET to an active logic 1 in response to the transition of UP. At time t4, UP and DOWN transition back to an inactive logic 0 such that the overcorrection period between t2 and t4 is approximately 0.8 ns, the same duration as discussed above in conjunction with FIG. 3 where the feedback signal is in phase with REF. Consequently, the overcorrection period, which here extends the length of DOWN beyond that which is necessary to correct the phase of the feedback signal, may cause the charge pump 40 to introduce a noticeable phase error into OSC1 and OSC2 as discussed above. At time t5, the AND gate 38 transitions RESET back to an inactive logic 0 to end the phase-correction cycle.